publications

Publications from the ICE Lab at Drexel University.

Google Scholar Profile: Ioannis Savidis

Tutorials

  1. Machine Learning for Automated Physical Design
    I. Savidis and P. Shrestha
    In 2025 IEEE International Conference on Computer Design, 2025
  2. Emerging ML-AI Techniques for Analog EDA
    I. Savidis
    In 2025 IEEE International Symposium on Circuits and Systems, 2025
  3. Machine Learning for Digital Design Automation
    I. Savidis and P. Shrestha
    In 2024 IEEE International Symposium on Circuits and Systems, 2024
  4. Emerging ML-AI Techniques for Analog EDA
    I. Savidis
    In 2023 IEEE International Symposium on Circuits and Systems, 2023

Book

  1. Three-Dimensional Integrated Circuit Design, 2nd Edition
    V. Pavlidis, I. Savidis, and E. G. Friedman
    2017
    521 Google Scholar citations

Book Chapter

  1. Physical Design Trends for Interconnects
    I. Savidis and E. G. Friedman
    In On-Chip Communication Architectures System on Chip Interconnect, 2008
    1 Google Scholar citations

Dissertations

  1. Enhancing Analog Circuit Security Through Obfuscation
    Vaibhav Venugopal Rao
    Drexel University, 2024

Journal Papers

  1. Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array
    Z. Chen and I. Savidis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025
    2 Google Scholar citations
  2. Hidden Costs of Analog Deobfuscation Attacks
    V. V. Rao, K. Juretus, and I. Savidis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023
    9 Google Scholar citations
  3. Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
    V. V. Rao and I. Savidis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021
    21 Google Scholar citations
  4. Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators
    M. S. Hossain and I. Savidis
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2021
    3 Google Scholar citations
  5. Synthesis of Hidden State Transitions for Sequential Logic Locking
    K. Juretus and I. Savidis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
    23 Google Scholar citations
  6. Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking
    K. Juretus and I. Savidis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
    20 Google Scholar citations
  7. Physical Layer Encryption for Wireless OFDM Communication Systems
    M. Jacovic, K. Juretus, N. Kandasamy, and 2 more authors
    Journal of Hardware and Systems Security, 2020
    20 Google Scholar citations
  9. Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
    K. Juretus and I. Savidis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
    12 Google Scholar citations
  10. Recycling of Unused Leakage Current for Energy Efficient Multi-voltage Systems
    M. S. Hossain and I. Savidis
    Microelectronics Journal, 2020
    5 Google Scholar citations
  11. Securing Wireless Communication via Hardware-based Packet Obfuscation
    J. Chacko, K. Juretus, M. Jacovic, and 4 more authors
    Journal of Hardware and Systems Security, 2019
    4 Google Scholar citations
  12. On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors
    D. Pathak and I. Savidis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
    7 Google Scholar citations
  13. ElasticCore: A Dynamic Heterogeneous Platform with Joint Core and Voltage/Frequency Scaling
    M. K. Tavana, M. H. Hajkazemi, D. Pathak, and 2 more authors
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
    8 Google Scholar citations
  14. Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery
    D. Pathak, H. Homayoun, and I. Savidis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
    22 Google Scholar citations
  15. Heterogeneous 3-D Circuits: Integrating Free-Space Optics with CMOS
    I. Savidis, B. Ciftcioglu, J. Xu, and 10 more authors
    Microelectronics Journal, 2016
    10 Google Scholar citations
  16. Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits
    I. Savidis, B. Vaisband, and E. G. Friedman
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015
    26 Google Scholar citations
  17. Power Noise in TSV-Based 3-D Integrated Circuits
    I. Savidis, S. Kose, and E. G. Friedman
    IEEE Journal of Solid-State Circuits, 2013
    31 Google Scholar citations
  18. 3-D Integrated Heterogeneous Intra-Chip Free-Space Optical Interconnect
    B. Ciftcioglu, R. Berman, S. Wang, and 8 more authors
    Optics Express, 2012
    68 Google Scholar citations
  19. Clock Distribution Networks in 3-D Integrated Systems
    V. Pavlidis, I. Savidis, and E. G. Friedman
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
    68 Google Scholar citations
  20. Thermal Analysis of Oxide-Confined VCSEL Arrays
    J. Wang, I. Savidis, and E. G. Friedman
    Microelectronics Journal, 2011
    49 Google Scholar citations
  21. A 3-D Integrated Intra-Chip Free-Space Optical Interconnect for Many-Core Chips
    B. Ciftcioglu, R. Berman, J. Zhang, and 12 more authors
    IEEE Photonics Technology Letters, 2011
    46 Google Scholar citations
  22. Electrical Modeling and Characterization of Through-Silicon vias (TSVs) for 3-D Integrated Circuits
    I. Savidis, S. M. Alam, A. Jain, and 3 more authors
    Microelectronics Journal, 2010
    99 Google Scholar citations
  23. Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance
    I. Savidis and E. G. Friedman
    IEEE Transactions on Electron Devices, 2009
    261 Google Scholar citations
  24. Characterization of Josephson Junctions
    I. Savidis and R. Sobolewski
    University of Rochester Journal, 2000

Conference Papers

  1. Representation Learning for Digital Integrated Circuit Design Automation
    P. Shrestha and I. Savidis
    In Proceedings of the IEEE International Conference on Computer Design (ICCD), 2025
    0 Google Scholar citations
  2. Differentiable Graph Neural Networks for Wirelength Estimation
    Z. Wu, P. Shrestha, S. Phatharodom, and 1 more author
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2025
    1 Google Scholar citations
  3. EDA-schema: A graph datamodel schema and open dataset for digital design automation
    P. Shrestha, A. Aversa, S. Phatharodom, and 1 more author
    In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2024
    20 Google Scholar citations
  4. Transfer learning of arrival time prediction models from a 65 nm to a 28 nm process node
    P. Shrestha and I. Savidis
    In Proceedings of the IEEE Conference Dallas Circuits and Systems (DCAS) Conference, 2024
    0 Google Scholar citations
  5. EDA-ML: Graph representation learning framework for digital IC design automation
    P. Shrestha and I. Savidis
    In Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2024
    14 Google Scholar citations
  6. Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect
    P. Shrestha and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2023
    7 Google Scholar citations
  7. Modeling Graph Neural Networks for Gate Level Arrival Time Prediction of Long Tailed Datasets
    P. Shrestha, S. Phatharodom, and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2023
  8. Graph Representation Learning for Gate Arrival Time Prediction
    P. Shrestha, S. Phatharodom, and I. Savidis
    In Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2022
    20 Google Scholar citations
  9. Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking
    P. Shrestha and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2022
    1 Google Scholar citations
  10. Reconfigurable Analog Array for Hardware Security
    Z. Chen and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2022
    2 Google Scholar citations
  11. Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits
    V. V. Rao, A. Sasan, and I. Savidis
    In Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), 2022
    12 Google Scholar citations
  12. Adaptive-Gravity: A Defense Against Adversarial Samples
    A. Mirzaeian, Z. Tian, S. Manoj, and 4 more authors
    In Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), 2022
    5 Google Scholar citations
  13. Implementation of Analog Systems on a Reconfigurable Array
    Z. Chen and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2022
    1 Google Scholar citations
  14. Reconfigurable Array for Analog Applications
    Z. Chen and I. Savidis
    In Proceedings of the IEEE International Conference on Computer Design (ICCD), 2021
    4 Google Scholar citations
  15. Variation-aware Analog Circuit Sizing with Classifier Chains
    Z. Wu and I. Savidis
    In Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2021
    8 Google Scholar citations
  16. Energy Efficient Computing with Heterogeneous DNN Accelerators
    M. S. Hossain and I. Savidis
    In Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021
    3 Google Scholar citations
  17. SAT-attack Resilience Measure for Access Restricted Circuits
    S. Phatharodom, A. Sasan, and I. Savidis
    In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021
    0 Google Scholar citations
  18. A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop
    S. A. Beheshti, A. Vakil, S. Manoj, and 3 more authors
    In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021
    9 Google Scholar citations
  19. CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing
    Z. Wu and I. Savidis
    In Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2020
    5 Google Scholar citations
  20. Security Vulnerabilities of Obfuscated Analog Circuits
    V. V. Rao, K. Juretus, and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020
    18 Google Scholar citations
  21. Reducing Logic Locking Key Leakage Through the Scan Chain
    K. Juretus and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020
    3 Google Scholar citations
  22. Modeling SAT-attack Search Complexity
    S. Phatharodom, N. Kandasamy, and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020
    5 Google Scholar citations
  23. Dynamic Idle Core Management and Leakage Current Reuse in MPSoC Platforms
    M. S. Hossain and I. Savidis
    In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020
    2 Google Scholar citations
  24. Closed-form Estimation of SAT-Attack Resilience
    S. Phatharodom, N. Kandasamy, and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2020
    2 Google Scholar citations
  25. Multi-Objective Simulation-based Optimization of Analog Transistor Sizing
    V. V. Rao and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2020
    1 Google Scholar citations
  26. Applying Swarm Intelligence to Distributed On-Chip Power Management
    D. Pathak and I. Savidis
    In Proceedings of the IEEE International Conference on Computer Design (ICCD), 2019
    0 Google Scholar citations
  27. Evolving On-Chip Power Delivery through Particle Swarm Optimization
    D. Pathak and I. Savidis
    In Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2019
    1 Google Scholar citations
  28. Robust Low Power Clock Synchronization for Multi-Die Systems
    R. Kuttappa, B. Taskin, S. Lerner, and 2 more authors
    In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019
    10 Google Scholar citations
  29. Mesh Based Obfuscation of Analog Circuit Properties
    V. V. Rao and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2019
    33 Google Scholar citations
  30. Increasing the SAT Attack Resiliency of In-Cone Logic Locking
    K. Juretus and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2019
    19 Google Scholar citations
  31. Reusing Leakage Current for Improved Energy Efficiency of Multi-voltage Systems
    M. S. Hossain and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2019
    9 Google Scholar citations
  32. Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies
    K. Juretus, V. V. Rao, and I. Savidis
    In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2019
    23 Google Scholar citations
  33. Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery
    M. S. Hossain and I. Savidis
    In Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC), 2018
    4 Google Scholar citations
  34. Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory
    V. V. Rao and I. Savidis
    In Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
    7 Google Scholar citations
  35. Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security
    K. Juretus and I. Savidis
    In Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
    12 Google Scholar citations
  36. Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures
    D. Werner, K. Juretus, I. Savidis, and 1 more author
    In Proceedings of the IEEE International Conference on Computer Design (ICCD), 2018
    4 Google Scholar citations
  37. A Quasi-Analytic Behavioral Model for the Single-electron Transistor for Hybrid MOS/SET Circuit Simulation
    F. Castro, I. Savidis, and A. Sarmiento
    In Proceedings of the IEEE Nanotechnology Materials and Devices Conference (NMDC), 2018
    7 Google Scholar citations
  38. Time Domain Sequential Locking for Increased Security
    K. Juretus and I. Savidis
    In Proceedings of the International Symposium on Circuits and Systems (ISCAS), 2018
    21 Google Scholar citations
  39. Noise Constrained Optimum Selection of Supply Voltage for IoT Applications
    M. S. Hossain and I. Savidis
    In Proceedings of the International Symposium on Circuits and Systems (ISCAS), 2018
    3 Google Scholar citations
  40. Enhanced Circuit Security Through Hidden State Transitions
    K. Juretus and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2018
    4 Google Scholar citations
  41. Security Oriented Analog Circuit Design Using Satisfiability Modulo Theory Based Search Space Exploration
    V. V. Rao and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2018
    2 Google Scholar citations
  42. Power Conversion Efficiency-aware Mapping of Multithreaded Applications on Heterogeneous Architectures: A Comprehensive Parameter Tuning
    H. Sayadi, D. Pathak, I. Savidis, and 1 more author
    In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2018
    25 Google Scholar citations
  43. Bi-directional Input/Output Circuits with Integrated Level Shifters for Near-Threshold Computing
    M. S. Hossain and I. Savidis
    In Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
    7 Google Scholar citations
  44. Clock Tree Synthesis for Heterogeneous 3-D Integrated Circuits
    I. Daulagala and I. Savidis
    In Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2017
    1 Google Scholar citations
  45. Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery
    D. Pathak, H. Homayoun, and I. Savidis
    In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2017
    13 Google Scholar citations
  46. Protecting Analog Circuits with Parameter Biasing Obfuscation
    V. V. Rao and I. Savidis
    In Proceedings of the IEEE Latin American Test Symposium (LATS), 2017
    55 Google Scholar citations
  47. Physical Gate Based Preamble Obfuscation for Securing Wireless Communication
    J. Chacko, K. Juretus, M. Jacovic, and 4 more authors
    In Proceedings of the International Conference on Computing, 2017
    13 Google Scholar citations
  48. A Framework for Exploring Alternative Fault-Tolerant Schemes Targeting 3-D Reconfigurable Architectures
    K. Siozios, I. Savidis, and D. Soudris
    In Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, 2016
    5 Google Scholar citations
  49. Reducing Logic Encryption Overhead Through Gate Level Key Insertion
    K. Juretus and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
    31 Google Scholar citations
  50. Robust Near-Threshold Inverter with Improved Performance for Ultra-Low Power Applications
    M. S. Hossain and I. Savidis
    In Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
    7 Google Scholar citations
  51. Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering
    D. Pathak, M. Hajkazemi, M. Tavana, and 2 more authors
    In Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
    6 Google Scholar citations
  52. Reduced Overhead Gate Level Logic Encryption
    K. Juretus and I. Savidis
    In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2016
    44 Google Scholar citations
  53. Load Balanced On-Chip Power Delivery for Average Current Demand
    D. Pathak, M. Hajkazemi, M. Tavana, and 2 more authors
    In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2016
    6 Google Scholar citations
  54. Low Overhead Gate Level Logic Encryption
    K. Juretus and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2016
    0 Google Scholar citations
  55. Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing
    M. S. Hossain and I. Savidis
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2016
    2 Google Scholar citations
  56. Securing Integrated Circuits Through Gate-Level Logic Encryption
    Juretus and I. Savidis
    In ” 2015 Defense Innovation Summit, 2015
  57. Realizing Complexity Effective On Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping
    M. Tavana, D. Pathak, M. Hajkazemi, and 2 more authors
    In Proceedings of the International Conference on Computer Design, 2015
    11 Google Scholar citations
  58. ElasticCore: Enabling Dynamic Heterogeneity With Joint Core and Voltage/Frequency Scaling
    M. K. Tavana, M. H. Hajkazemi, D. Pathak, and 2 more authors
    In Proceedings of the IEEE/ACM Design Automation Conference (DAC), 2015
    29 Google Scholar citations
  59. Power Supply Voltage Detection and Clamping Circuit for 3-D Integrated Circuits
    D. Pathak and I. Savidis
    In Proceedings of the IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2014
    1 Google Scholar citations
  60. Run-Time Voltage Detection Circuit for 3-D IC Power Delivery
    D. Pathak and I. Savidis
    In Proceedings of the IEEE International System-on-Chip (SoC) Conference, 2014
    3 Google Scholar citations
  61. Thermal Conduction Path Analysis in 3-D ICs
    B. Vaisband, I. Savidis, and E. G. Friedman
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    21 Google Scholar citations
  62. Thermal Coupling in TSV-Based 3-D Integrated Circuits
    I. Savidis and E. G. Friedman
    In Proceedings of the Workshop on 3-D Integration, 2014
    3 Google Scholar citations
  63. Test Circuits for 3-D Systems Integration
    I. Savidis and E. G. Friedman
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2012
    0 Google Scholar citations
  64. Chip-Scale Demonstration of 3-D Integrated Intra-Chip Free-Space Optical Interconnect (Invited Paper)
    H. Wu, B. Ciftcioglu, R. Berman, and 8 more authors
    In ” Photonics West: SPIE Optoelectronic Integrated Circuits XIV, 2012
    10 Google Scholar citations
  65. Clock Distribution Models of 3-D Integrated Systems
    I. Savidis, V. Pavlidis, and E. G. Friedman
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2011
    4 Google Scholar citations
  66. Power Grid Noise in TSV-Based 3-D Integrated Systems
    I. Savidis, S. Kose, and E. G. Friedman
    In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 2011
    6 Google Scholar citations
  67. Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect
    B. Ciftcioglu, R. Berman, J. Zhang, and 13 more authors
    In Proceedings of the Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS 2010), 2010
    0 Google Scholar citations
  68. An Intra-Chip Free-Space Optical Interconnect
    J. Xue, A. Garg, B. Ciftcioglu, and 11 more authors
    In Proceedings of the Annual International Symposium on Computer Architecture (ISCA), 2010
    112 Google Scholar citations
  69. 3-D Integrated Intra-Chip Free-Space Optical Interconnect
    B. Ciftcioglu, R. Berman, J. Zhang, and 12 more authors
    In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) Student Research Forum, 2010
  70. An Intra-Chip Free-Space Optical Interconnect
    J. Xue, A. Garg, B. Ciftcioglu, and 9 more authors
    In Proceedings of the 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI ‘ 09), 2009
    112 Google Scholar citations
  71. Clock and Power Distribution Networks for 3-D Integrated Circuits
    I. Savidis, E. G. Friedman, V. F. Pavlidis, and 1 more author
    In Proceedings of the Workshop on 3D Integration, 2009
    2 Google Scholar citations
  72. Electrical Modeling and Characterization of Through-Silicon vias (TSVs) for 3-D Integrated Circuits
    I. Savidis, S. M. Alam, A. Jain, and 3 more authors
    In Proceedings of VLSI/ULSI Multilevel Interconnect Conference (VMIC), 2008
    99 Google Scholar citations
  73. Clock Distribution Architectures for 3-D SOI Integrated Circuits
    V. F. Pavlidis, I. Savidis, and E. G. Friedman
    In Proceedings of the IEEE International SOI Conference, 2008
    7 Google Scholar citations
  74. Clock Distribution Networks for 3-D Integrated Circuits
    V. F. Pavlidis, I. Savidis, and E. G. Friedman
    In Proceedings of the IEEE Custom Integrated Circuits Conference, 2008
  75. Electrical Modeling and Characterization of 3-D Vias
    I. Savidis and Eby G. Friedman
    In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2008
    82 Google Scholar citations

Pre-prints

  1. EDA-Schema-V2: A Multimodal Schema, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design
    P. Shrestha, A. Aversa, and I. Savidis
    arXiv preprint arXiv:2605.06952, 2026
    0 Google Scholar citations
  2. Deep Representation Learning for Electronic Design Automation
    P. Shrestha, S. Phatharodom, A. Aversa, and 3 more authors
    arXiv preprint arXiv:2505.02105, 2025
    1 Google Scholar citations
  3. Emerging ML-AI Techniques for Analog and RF EDA
    Z. Wu, Z. Chen, N. Achebe, and 3 more authors
    arXiv preprint arXiv:2506.00007, 2025
    3 Google Scholar citations

Workshop Presentations

  1. On-Chip Power Delivery
    I. Vaisband, S. Kose, I. Savidis, and 1 more author
    2011
  2. Clock Distribution Topologies for 3-D Integrated Circuits
    I. Savidis and E. G. Friedman
    2009
  3. Clock Distribution Networks for 3-D Integrated Circuits
    V. F. Pavlidis, I. Savidis, and E. G. Friedman
    2008
  4. Electrical Modeling and Characterization of 3-D Vias
    I. Savidis and E. G. Friedman
    2008

Conference Presenter

  1. Clock Distribution Models of 3-D Integrated Systems
    I. Savidis
    2011
  2. Power Grid Noise in TSV-Based 3-D Integrated Systems
    I. Savidis
    2011
  3. Clock Distribution and Power Delivery for 3-D Integrated Circuits
    I. Savidis
    2009
  4. Clock Distribution Architectures for 3-D SOI Integrated Circuits
    I. Savidis
    2008
  5. Electrical Modeling and Characterization of 3-D Vias
    I. Savidis
    2008
  6. Clock and Power Distribution Networks for Three-Dimensional Circuits: Preliminary Design Review
    I. Savidis
    2006

Technical Industrial Presentations

  1. 3-D Test Circuit on Power Delivery
    I. Savidis
    2012
  2. Recent Research in 3-D Circuit Design and Related Test Circuits
    I. Savidis
    2011
  3. Recent Research in 3-D Circuit Design and Related Test Circuits
    I. Savidis
    2011
  4. Lessons Learned in 3-D Verification
    I. Savidis
    2008