Thermal Modeling and Mitigation

Two of the most omnipresent and challenging issues in high performance 3-D systems are power delivery and thermal management. The interdependence of these issues is of critical importance to 3-D systems, as noise on the power network can produce severe hot spots within a 3-D stack. Enhanced understanding of these interrelated 3-D design challenges is therefore necessary to develop design techniques and methodologies to effectively deliver power while managing thermal effects. Thermal effects can potentially alter the performance of the clock and power networks due to hot spots. A test circuit has been fabricated by Tezzaron Semiconductor in a 130 nm CMOS technology with 1.2 micrometers. A face-to-face bonding technique to vertically stack two logic device planes has been implemented by Tezzaron. Test structures have been developed to evaluate thermal coupling within 3-D systems. This test circuit is designed to better understand the effects of inter- and intra-plane thermal resistances on hot spot formation. We have also examined the thermal impact that bundled VCSELs have in a 3-D stack, as the top surface usually utilized by a heat sink is now occupied by photonic devices. Thermal models of the two-tiered CMOS planes were developed in Hot Spot to compare with the experimental results, and to explore mitigation techniques of thermal hot spots.