TSV Modeling and Characterization

The critical component of a 3-D IC is the through-silicon via. Our seminal work on the electrical characterization of the TSV resistance, capacitance, and inductance as a function of the diameter, length, dielectric thickness, and material properties of the silicon, dielectric, and metal fill initiated a slew of work on further characterizing the TSV for high frequency, different TSV placement topologies, and different physical phenomena such as depletion region formation around the TSV and interface charge trapping, which impact the TSV capacitance. Once the TSV was characterized via full wave simulation, closed-form expressions for the TSV resistance, capacitance, and inductance were developed. The closed-form expressions were compared to the simulated results, producing errors of less than 8% for the resistance, capacitance, and inductance across all diameters, lengths, dielectric thicknesses, and for frequencies upto ten GHz. An equivalent pi-model of the TSV was developed based on the closed-form expressions for TSVs produced by MIT Lincoln Laboratory and Tezzaron Semiconductor. The pi-model representation of the TSV was used for both modelling and spice analysis of the 3-D clock and power delivery networks further discussed below.