3-D Integrated Circuit Power Delivery

An important issue for 3-D integrated circuits is the design of a robust power distribution network that can provide sufficient current to every load within a system. Power delivery in 3-D integrated systems presents difficult new challenges for delivering sufficient current to each device plane. Stacking device planes in the vertical direction leads to higher power densities. Specialized techniques are required to ensure that each device plane is operational, while not exceeding the target output impedance. The focus of our research is on a primary issue in 3-D power delivery, the power distribution network, and provides a quantitative experimental analysis of the noise measured on each plane within a three plane 3-D integrated stack. A three-dimensional (3-D) test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers were vertically bonded to form a 3-D stack. Three topologies to distribute power within a 3-D circuit have been evaluated, and an analysis of the peak noise voltage, voltage range, average noise voltage, and resonant frequency characteristics for both power and ground was performed. The effect of the through silicon via (TSV) density on the noise profile of a 3-D power delivery network is experimentally described. A comparison of the peak noise for each topology with and without board level decoupling capacitors, and resonant behavior are provided, and suggestions for enhancing the design of a 3-D power delivery network were offered. Models of the three power distribution topologies were developed and peak noise voltage and resonant frequency characteristics were compared with experimental results. This test circuit provided enhanced understanding of topology dependent noise generation and propagation in 3-D power delivery systems.