Attack Prevention Through Design for Trust Algorithms and Methodologies

EDA tools used for circuit design implement algorithms and methodologies that account for the power, area, and performance of the many blocks comprising the IC. With the more recent threat of untrusted hardware and side-channel attacks, the circuit design paradigm must now also include security as an additional parameter. My research group is therefore developing algorithms for hardware security that can then be integrated with traditional techniques that account for the power, area, and performance of a circuit. We are also developing algorithms and circuit methodologies that will allow for the automated insertion of hardware security measures into many varieties of IC designs based on the desired level of security. A security metric is being developed that, given an implemented security measure, will provide a means to measure both the gains in security and the costs in design space (area, power, and performance). In addition, algorithms to determine the optimal location and number of sensors for a given design based on a user specified level of security (level of granularity of Trojan detection) are required to effectively implement the run-time detection of hardware Trojans.