research

Power delivery, synchronization, and signaling for TSV-based and heterogeneous 3-D stacks. The lab's seminal TSV electrical models, fabricated multi-plane test circuits, thermal analysis, and free-space optical interconnects established early ground work for three-dimensional systems.

Securing integrated circuits against hardware Trojans, IP piracy, and reverse engineering. The group develops logic locking and analog parameter obfuscation, SAT-attack resilience analysis, and run-time detection with countermeasures - the subject of a 2018 NSF CAREER award.

Graph neural networks that predict expensive late-stage chip metrics - timing, parasitics, wirelength - from early design stages, transfer learning across technology nodes, and the open EDA-Schema data infrastructure and benchmarks that make ML-for-EDA results reproducible.

Operating circuits near the transistor threshold voltage for quadratic power savings, then recovering performance with dynamic current-mode logic. The group designs resilient near-threshold circuits and methodologies that trade off power and throughput.